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ISP-8A/600 single-chip 8-bit n-channel microprocessor (SC/MP-II) This document transcribed by Paul Robson (autismuk@aol.com). Some details and illustrations have been omitted (but are available if required). A briefer introduction to this chip is here. general description SC/MP (Simple Cost-effective MicroProcessor) is a single-chip 8-bit microprocessor packaged in a standard 40 pin dual-in-line package. N-channel, silicon gate, depletion mode standard process technology ensures high performance, high reliability and high producibility. SC/MP is intended for use in general-purpose applications where cost per function is a most significant criterion. But cost efficiency is only a part of SC/MP's story. It goes on to include a variety of useful functions that are not even provided by some of the expensive microprocessors, like self-contained timing circuitry, 16-bit (65k) addressing capability, serial or parallel data-transfer capability and common memory / peripheral instructions. The built in features in conjunction with the low initial cost describe what SC/MP real is - a microprocessor specifically designed to provide the simplest and most efficient solution to many application requirements. customer benefits
applications
ratings & electrical characteristics not yet available functional description SC/MP is a self contained general purpose microprocessor designed for ease of implementation in stand-alone DMA (Direct Memory Access) and multiprocessor applications. Communications between SC/MP and external memory/address devices are effected via a 12-bit dedicated address bus and an 8 bit bidirectional data bus. During the address interval of each input/output cycle, SC/MP employs both busses to provide a 16-bit address output : the 12 least significant address bits are sent out over the 12-bit address bus and the 4 most significant address bits are sent out over the 8 bit data bus along with 4 status bits. Separate strobe outputs from SC/MP (NADS,NWDS,NRDS indicate when valid address information is present on the two busses and when valid input/output memory or peripheral data are present on the 8-bit bus. To further extend flexibility of application serial data input/output ports are also provided so the serial data transfers can be effected under program control. The remaining input/output signals are dedicated to general purpose control and status functions, including initialisation, bus management, microprocessor halt, interrupt request, input/output cycle extension and user-specified hardware / software interface functions. A detailed description of each input/output signal is provided in table 1.
Note: The 8 bit bidirectional data bus is set to the high impedance (tristate) mode except when it is actually in use by SC/MP (NADS,NRDS or NWDS low). During the addressing interval of each input/output cycle (NADS low), SC/MP provides address and status outputs over the bus ; during the ensuing data transfer interval (NRDS or NWDS low) 8 bit input or output data bytes are routed over the bus. drivers and receivers Equivalent circuits for SC/MP drivers and receivers are shown below. All inputs have static charge protection circuits consisting of an RC filter and voltage clamp. These devices should still be handled with care, as the protection circuits can be destroyed by excessive static charge. timing control All necessary timing singles are provided by a three stage inverter ring oscillator contained on the SC/MP chip. Two control pins, XIN and XOUT permit the frequency of the oscillator to be controlled by any of the following methods:
In the discussions that follow, instruction execution and input/output timing are described in terms of microcycles. The time interval of a microcycle is four times the period of the oscillator. instruction format The SC/MP instruction repertoire includes both single and double byte instructions. A single byte instruction consists of an 8-bit operation code that specifies an operation that SC/MP can execute without further reference to memory> A double byte instruction consists of an 8 bit operation code and an 8 bit data or displacement field. When the second byte represents a data field, the data are processed by SC/MP during execution of the instruction, thereby eliminating the need for further memory references. When the second byte represents a displacement value it is used to calculate a memory address that will be accessed (written into or read from) during execution of the instruction (refer to addressing). data storage SC/MP provides ten internal registers, seven of which are accessible to the programmer. The purpose and function of these registers are described below: Program Counter - The program counter is a 16 bit register that contains the address of the instruction being executed. The contents of this register are automatically incremented by one just before each instruction is fetched form memory to enable sequential execution of the stored instructions. Under program control, the contents of this register also may be modified or exchanged with the contents of a pointer register to effect subroutine calls and program branches. NOTE: The 16 bit address output of the program counter consists of a 4 bit high order address and a 12 bit low order address. When the program counter is incremented at the start of each instruction fetch cycle, only the 12 low order bits are affected; no carry is provided to the 4 high order bits. For systems employing memories of 4k or less, the high order bits can be ignored as they are set to 0000 following initialisation. For systems employing larger memories, the contents of a pointer register can be modified to select the desired 4k block of memory Pointer Registers - the pointer registers are 16-bit general purpose registers that normally are loaded under program control with reference addresses that serve as page pointers, stack pointers and subroutine pointers. In applications having minimal memory addressing requirements, these registers may be used alternately as data storage registers. NOTE: When interrupt requests are enabled, pointer register 3 is automatically referenced by the internal microprogram for formation of the starting address of the user generated interrupt service routine. In this case, the contents of pointer register 3 must be set arithmetic and logic unit not yet available bus transfer logic not yet available status register not yet available control not yet available initialisation not yet available parallel data transfers not yet available bus utilization not yet available bus access not yet available input/output cycle not yet available input/output cycle extension not yet available serial data transfers not yet available interrupt not yet available microprocessor halt not yet available instruction set not yet available system implementation |