000-1FF	512 byte SCIOS ROM	Decoded by 0xxx
200-3FF	ROM Shadow / Expansion RAM
400-5FF	ROM Shadow / Expansion RAM
600-7FF	ROM Shadow / Expansion RAM
800-87F	128 bytes I/O chip RAM	Decoded by 1xx0
880-8FF	I/O Ports	Decoded by 1xx0
900-9FF	Keyboard & Display	Decoded by 1x01
A00-AFF	I/O Port & RAM Shadow
B00-BFF	256 bytes RAM (Extended) / VDU RAM	Decoded by 1011
C00-CFF	I/O Port & RAM Shadow
D00-DFF	Keyboard & Display Shadow
E00-EFF	I/O Port & RAM Shadow
F00-FFF	256 bytes RAM (Standard) / VDU RAM	Decoded by 1111

Keyboard Decoding

On a READ the switch levels are read onto the bus via IC11 into bits D4-D7

On a WRITE the bits D0-D7 are latched (sort of !) via IC9 and IC10 into the video display latches (D0=Segment A,D7 = Decimal Point)

On any Access the lower 4 address bits are latched into IC12. These are decoded by IC13, dragging the appropriate line low to light the segments selected via IC9 and IC10

IC11 is normally read as 1111xxxx - if a key is pressed when the corresponding line is pulled low via IC13 then bits will be read as zero - this indicates a key is being pressed.

RAM Expansion

It is a standard Sinclair design that the 3 ROM Shadows between 0200 and 07FF can be replaced by RAM, giving a theoretical total of 1.5k (expansion) 1/4k (extended) 1/8k (RAM I/O Chip) 1/4k (Standard)